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Re: [Amps] Duty cycle for processed SSB in contest conditions?

To: amps@contesting.com
Subject: Re: [Amps] Duty cycle for processed SSB in contest conditions?
From: Steve Thompson <g8gsq72@gmail.com>
Date: Sun, 23 Feb 2014 09:25:16 +0000
List-post: <amps@contesting.com">mailto:amps@contesting.com>
For class AB amplifiers I have a rule of thumb (which got named after me at one place I worked) - for output powers from 10% to P1dB device dissipation is roughly constant.

Tx/rx duty cycle - we used to hit 80% when calling CQ during the small hours in VHF events.

Steve

Can anyone suggest what the duty cycle for sensibly processed
SSB would be during contest conditions? When an LD-MOS PA is
backed off to achieve good linearity then the efficiency
reduces from 80% at P3dB for CW or 100% duty cycle data modes
down to around 65% for IMD3 of better than -30dBc. The thermal
impact of this is quite severe and I am trying to calculate
what is acceptable for SSB during a typical contest. Personally
I am looking at 6m and above but it holds true for HF
amplifiers as well.


I know that it is difficult to say what the ratio of TX/RX time
is but lets be pessimistic.

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