Angel,
I built your ESR meter last year, and right away, it allowed me to
repair several SMPS I had collected over the years!
Good! It's a really useful gadget.
OK, since it is a push-pull, the calculation must be done with twice
the supply voltage. I did not tnink of that.
Yes, basically that's it.
But could it also be said, as you wrote on this page of your website:
https://ludens.cl/Electron/mosfetamps/amps.html
"When Q1 conducts at the peak of its semicycle, it will have 1.3V on
its drain, making 12.5V between Vcc and its drain. That places 12.5V
on one half of T2. Due to the tight coupling, that forces 25V to
appear across the entire T2, making Q2's drain go up to 26.3V. The
primaries of T1 will see a total of 25V."
Or are these two ways to express in fact the same phenomenon?
Yes, it's the same thing. The 1.3V in that example depends on the
tarnsistrs chosen, and the operating conditions, such as current and
frequency. It also depends on how much compression (distortion) you are
willing to accept. So that number is not fixed at all. But whatever it
is, you can plug it into the equation and then calculate the power
output you should get.
>Also, the other thing I could not understand was the high output
>impedance that the author of the project claims: 42 ohms.
He says 48 ohm, but that's not entirely correct. The impedance at which
the transistors are loaded is simply the impedance of the load (antenna
or whatever), transformed by the lowpass filter (ideally the filter
should reflect the same impedance). So, if the filter is optimal, and
you are transmitting into a 50 ohm dummy load, those same 50 ohm appear
as the load between drains, given teh fact that there is just a 1:1
balun in between.
>As Bill Turner writes in another post: "The output impedance of the amp
>should be very small, close to zero and the load impedance around 50
>ohms. "
Bill is right.
>That is exactly what I thought too!
>Instead, this amp uses no output transformer, only a 1:1 balun. How can
>this possibly work?
I see that you still don't understand the difference between output
impedance and load impedance. So here is the explanation:
Output impedance is truly the impedance you would measure if you
replaced the load by an impedance meter and measured into the
amplifier's output. Instead load impedance is the impedance of the load,
and load impedance to the transistors is the load you and the circuit
apply to the transistors. The two don't need to match, and in fact in
power amplifiers they SHOULD NOT match, because if they match then the
efficiency will be terrible!
When the output and load impedances match, you get the highest possible
power from a circuit. But nothing guarantees that the power source
(amplifier) will not blow up under those conditions! Usually it would.
In the interest of efficiency, power amplifiers are normally designed in
such a way that the load impedance applied to them is much higher than
their internal output impedance, and the transistors and everything else
are dimensioned to handle the actual currents and powers that appear
under those operating conditions.
In pure theory, if you have an amplifier with a certain output
impedance, the behavior at different load impedances is:
Infinite load impedance: No power output, zero effficency.
High load impedance, compared to output impedance: Modest output power,
good efficiency, tending to approach the theoretical efficiency of the
amplifier class.
Load impedance equal to output impedance: Highest power output,
efficiency is only 50% of the theoretical efficiency of the operating class.
Low load impedance compared to output impedance: Modest output power,
very poor efficiency.
Zero load impedance: No output power, zero efficiency.
Now let's put some numbers to that small 2*IRF510 amplifier: For
simplest analysis let's assume square wave, fully saturated operation,
at a frequency so low that the FETs switch very cleanly. The RDSon of
that FET is given as 0.54 ohm. So during one half cycle you will have
one FET pulling its drain to ground via 0.54 ohm, and the other FET
open, and during the other half cycle the roles will reverse.
You have a 50 ohm dummy load, and let's assume that the lowpass filter
isn't there, or the frequency is so low that the filter passes the
strong harmonics. In that case the unaltered 50 ohm load appears between
drains. One drain is in open circuit, but that point is connected to the
bifiliar feed choke, which is really a 1:4 autotransformer. It will
transform the 50 ohm load down to 12.5 ohm and apply that to the
conducting FET. Since the FET has 0.54 ohm of internal resistance, the
total resistance from the power supply to ground is 13.04 ohm. If the
supply voltage is 13.8V, the supply current (and drain current of the
conducting FET) will be 1.058 amperes, and the input power will be
14.6W. Of this input power, 0.57W are dissipated in the FET, while the
bulk of the power, 14.03W, go to the load. Thus the efficiency is a very
high 96%, thanks to the load impedance being much higher than the output
impedance.
By the way, the output impedance is the 0.54 ohm of the conducting FET,
up-transformed in a 1:4 ratio by the bifiliar choke. So it's 2.16 ohm -
very low, as Bill said.
Now let's get a little more real: We are (hopefully) dealing with sine
waves. Saturation of a FET happens at best during the peak of the
waveform. This allows placing a lowpass filter of the proper band in the
circuit, but also makes the efficiency much lower. How much lower? Well,
instead of calculating impedances it's easier to calculate voltages and
currents. What was the effective voltage in the square wave example
becomes the peak voltage in a sine wave. That makes the RMS voltage
decrease to 0.71 of what it was before, and makes the output power one
half of what it was before. Thus we get 7W output, not 14W.
The RMS current in the sine wave is also 0.71 times that of the square
wave, so it's 0.751 A, but this is NOT the supply current! That's
because RMS does not equal average. There is roughly a 0.9 factor
between them. So the actual supply current is 0.676A, and at 13.8V, the
input power is 9.33W. With 7W output, the efficiency is now 75%. The
maximum theoretical efficiency of a class B amplifier is 78.5%, and in
our example it has dropped to 75% due to the non-zero output impedance
of the amplifier.
Now let's get another bit more real: MOSFETs unfortunately are not
linear. They are in fact extremely nonlinear! And switching MOSFETs like
the IRF510 are far more nonlinear than MOSFETs optimized for use in
linear amplifiers. To more or less linearize an amplifier using
switchmode MOSFETs, we need to do two things: Bias them for a strong
idling current, moving the operating point deep into class AB; and
applying strong negative feedback. The high idling current directly
reduces the efficiency (but not much the output power), while the
negative feedback eats a big chunk of the gain that would otherwise be
available, and consumes power in its resistors, thus also reducing the
efficiency. These are the main reasons why such amplifiers in practice
only get to roughly 50% efficiency. There is a trade-off to be made
between efficiency, linearity and gain, by juggling with the amount of
idling current and feedback.
And to get fully real, we need to consider that every component in the
circuit has loss, every conductor has inductance, the FETs have some
losses related to their limited speed, and all these things cost us both
output power and efficiency. Also throughout this analysis I have
thought of "impedance" as "resistance", but of course in RF circuits
impedances almost always include reactances, which make the detailed
analysis a bit more complicated. For example, waveforms at different
places of the circuit are no longer exactly in phase with each other,
and this effect increases as we raise the frequency.
A good question is what's the actual value of the amplifiers output
impedance is, when operating in its reasonably linear range rather than
in saturation. If the FETs were perfect, they would act as
voltage-controlled current sources. Thus, lacking any feedback, the
output impedance would be infinite, given that a change in drain voltage
would not cause any change in drain current. But FETs are not perfect,
and so they do have a finite impedance, which varies constantly along
the waveform.
If the amplifier had extremely strong negative feedback, then this
feedback network would basically stabilize the output voltage, making it
insensitive to output current changes. This would cause an output
impedance of zero! But of course, we cannot have infinite negative
feedback. The feedback can only be as large as the excess gain we have
available. The result is that negative feedback produces a lowish, but
definitely nonzero output impedance. Maybe the author stated the 48 ohm
output impedance based on the FET characteristics and the amount of
negative feedback he used, but such a calculation is imprecise and
unreliable, because FET transfer characteristics are only loosely
specified, and vary hugely with instantaneous drain current, frequency
and temperature. Even if the amplifier should have a (dynamic) output
impedance of 48 ohm under some specific conditions, and the load is 50
ohm, this is quite irrelevant regarding efficiency and power output. It
just means that the negative feedback is roughly 3dB under those conditions!
Since the linear mode output impedance is not useful in calculating the
efficiency, better use the method outlined above, and use the actual
currents and voltages rather than those calculated for a simplistic
approximation. But it's still useful to make such simplistic
approximations, to understand the basic situation.
Manfred
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