> I have seen FET gate bias in parallel schemes isolated by a diode to each
> FET.
> This would introduce a temperature gradient seemingly counter productive to
> stability.
>
> Can anyone explain it?
A very common failure mode when FETs blow is to go drain-gate
short. If bias feeds for multiple devices are tied together the
higher voltage fed into the network from the blown device can
apply excessive bias to the others, taking them out too.
A diode is one way to prevent this, and the temperature effect is
likely to be small for normal domestic temperature ranges. Since
there should be negligible current flowing into the gate, a series
resistor of 10s kohms could also be used giving a small 'reverse'
current which can be absorbed in something like a zener or bleed
resistor. Whatever scheme you choose, consider what happens if one
gate goes up to supply.
Steve
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