Can anyone suggest what the duty cycle for sensibly processed SSB would
be during contest conditions? When an LD-MOS PA is backed off to achieve
good linearity then the efficiency reduces from 80% at P3dB for CW or
100% duty cycle data modes down to around 65% for IMD3 of better than
-30dBc. The thermal impact of this is quite severe and I am trying to
calculate what is acceptable for SSB during a typical contest.
Personally I am looking at 6m and above but it holds true for HF
amplifiers as well.
I know that it is difficult to say what the ratio of TX/RX time is but
lets be pessimistic.
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73
Conrad G0RUZ IO93FR
North Wakefield Radio Club
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