Here are some things I think I know.
The voltage rating is high enough to handle 100% reflected with any phase
angle in 20% duty cycle pulse operation. Effectively, as long as the High
SWR trip can operation as fast the on pulse time, the amplifier is rugged
to 100% reflected. I forget the rep rate of the pulses, but the trip
circuit has 10's of msec.
Avalanche can occur unevenly across the die and result in uneven heating.
The power limit is not total dissipated, rather quite a bit less, due to
the risk of localized damage. An amp with fast trip will not need know the
details of that.
Body diodes in switching power supply MOSFETs are slow. LDMOS is
presumable the same. So, not fast enough for 100 KHZ switching PS and not
nearly fast enough for RF. A MOSFET with gate drive will conduct in both
directions, negative current is not a problem...presumably LDMOS is the
same. The classic low loss series FET switch in two in series with Sources
connect together. That switch is bilateral, with one FET always conducting
in reverse.
The FET can handle 100% reflected with any phase angle, one of those is max
drain current. Just stay within the pulse limits. The RF current does
not distribute evenly acoss the 1000's of parallel FETs, but over the
thermal time constant of the die, differential heating and negative temp
coefficient provides the feedback to balance the currents. But
instantaneously, localized heating can blow up a corner of the die.
I hope this helps.
jeff, wa1hco
On Sat, Nov 17, 2018 at 3:33 PM Manfred Mornhinweg <manfred@ludens.cl>
wrote:
> Hello,
>
> is there anyone on this forum who knows LDMOSFETs really well and could
> answer a few questions?
>
> My questions refer to a high power device like the BLF188XR or the
> MRF1K50N, operating in a broadband 1.8 to 30MHz amplifier, in saturated
> class AB, at about 6dB overdrive, into ham-typical loads, that is, a
> transmission-line transformer having a non-negligible line length, then
> a simple PI or T 5-pole lowpass filter, followed by a long transmission
> line and a real-world antenna, which could sometimes exhibit extreme SWR.
>
> Now the questions:
>
> 1. If a load happens to be such that drain voltage peaks in excess of
> VDSmax occur, to what extent can the LDMOSFET safely clamp these?
> Datasheets claim "high avalanche energy absorption capability", but
> don't tell how much it actually is. Working it out from the high SWR
> test data given in the datasheets is hard, since they are in pulsed
> service and refer to a specific circuit at a specific frequency and with
> low or no overdrive. What I want to know is whether or not such an
> LDMOSFET will survive all avalanching as long as the total dissipation
> doesn't result in overheating the silicon, or if the tolerable amount of
> avalanche power dissipation is lower, and if so, how much.
>
> 2. If load conditions are such that the drain voltage becomes negative
> for a part of the RF cycle, what will happen? How does the body diode of
> LDMOSFETs behave? Is it fast enough to safely clamp such negative
> spikes, or is it so slow that it will remain in conduction for a long
> time and cause extreme power dissipation from cross-conduction with the
> other side?
>
> 3. Why isn't the IDmax given in the datasheets of most LDMOSFETs? How
> can I know how much current an LDMOSFET can take, and for how long, in
> the event of severe load mismatch (short circuit)? This is quite
> important, in order to know how much I can overdrive such an amplifier.
>
>
> Manfred
>
>
>
> ========================
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> http://ludens.cl
> ========================
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