>> What sort of Vdd are you thinking of?
I am starting with 125V out of the buck converter. The VDD max of the parts
I am
using is 500V so I am not pushing this parameter at all. This supply voltage
is only a little over twice that of conventional RF parts so I am being
conservative.
Besides, 125V is easily available in our primitive land. I want to
eventually
try running at a little over 200V, but that is down the road
>>do you not have a problem with the input impedance dropping
>>because of Miller effect?
Yes, somewhat. I have gotten a good match with some smaller parts (Directed
Endergy)
up to 46Mhz using a transformer and a gate de-q resistor. VDD was 125V.
>>Most of the power FETs seem to have a pretty big input capacitance anyway
Yes 2500pF! on the Directed Energy parts, compared to 400pf on the MRF150.
The one I am using has a Crss of 25pF at 400VDS, so it comes to play, but a
bit
less than the MRF150 which is 40pF at 50VDS. International Rectifier wrote a
pretty good
spiel on gate charge computations that illustrates what you are talking
about quite
well.
>>Is there thus any advantage in considering using two FETs in a cascode in
>>each side of the push pull amp? It also gives a bit more Vdd margin.
Yes, definitely. One could use a conventional RF fet in this topology, or
maybe
a more exotic topology (push-pull on each side of a push pull?). The
downside, especially
for amateur applications is that the power supply situation may become more
complex.
>>Is it possible to absorb the input capacity by means of a suitable low
pass
>>network at the input with an impedance suitably low and a cut off
frequency
Interesting. I will be thinking about this a bit.
George K. Watson
K0IW
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