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[AMPS] Shunt regulated high voltage psu

To: <amps@contesting.com>
Subject: [AMPS] Shunt regulated high voltage psu
From: g8gsq@qsl.net (Steve Thompson)
Date: Tue, 29 Jan 2002 08:03:38 -0000

-----Original Message-----
From: Radio WC6W <wc6w@juno.com>
To: amps@contesting.com <amps@contesting.com>
To: <amps@contesting.com>
Date: 30 January 2002 18:32
Subject: Re: [AMPS] Shunt regulated high voltage psu


>
>
>On Wed, 30 Jan 2002 17:40:50 -0000 "Steve Thompson" <g8gsq@qsl.net>
>writes:
>
><snip>
>
>Hi Steve,
>
>> I'm going to have to build this up and hook the storage 'scope on!
>> The way I worked it was to assume 2kVish arcing to screen limited to
>about 40A
>> by a glitch resistor. This gives a time constant in the region of a
>couple of ms.
>> At the screen, the source impedance is quite low if there's 40A flowing
>and,
>> given that we want to keep the screen voltage stable at audio
>frequencies,
>> we should have a low impedance path to the regulator for a pulse of 2ms
>> upwards so I was expecting a lot of the 600V to arrive there with
>plenty of
>> current capacity, in which case the screen supply cap could end up with
>a
>> significant top up. If there's any significant capacitance hanging on
>the
>> gate/base of the series device, or if the control circuit tries to pull
>the
>> gate/base down to try and regain regulation even 10's V could be enough
>to
>> cause breakdown.
>
>   The screen bypass caps would necessarily have to be rated to survive
>whatever your MOV's will allow surgewise.
>
>   The pass FET should be OK in this instance.  You might want to add a
>small R in series with the FET drain to make the time constant long
>enough back into the screen supply cap (presumably 10-20uF) to side-step
>the surge.

I can visualise a scenario where the control circuit is pulling the gate
down because the o/p voltage is too high. Depending on the design, it might
pull to almost ground via a resistor, maybe it's only as low as 300V. If the
source is up at 5-600 because of the arc, the gate-source insulation will be
at risk. A high value g-s resistor won't protect if the resistance driving
the gate is much lower.
>
>   Incidentally, I typically solder a small 10V zener directly on my
>FET's (gate-source) to protect them when handling / prototyping.  This is
>good safety measure in any instance.
Yes, that would protect in several ways. I can see myself going down the
crowbar route, maybe with some extra capacitance at the screen to slow up
the rising edge.

Thanks, Marv.

Steve


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