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Re: [Amps] 2x LDMOS design tweaks

To: Jim Barber <>
Subject: Re: [Amps] 2x LDMOS design tweaks
From: Greg Wasik <>
Date: Tue, 10 Sep 2019 08:59:25 -0400
List-post: <>
Hi Jim,

I noticed that another Jim (W6PQL) had originally used the "drain to gate"
feedback in his earlier pallet design but went to a "gain shunt" approach.
You might want to ping him but I also found an interesting paper
"Stabilizing Mosfet Amps" by S.K. Leong.


On Mon, Sep 9, 2019 at 8:05 PM Jim Barber <> wrote:

> Since it's quiet out, here's my latest amp mod project... There's actually
> a question in the last paragraph. :-)
> Some time ago I bought a dual-package  MRFE6VP61K25HS LDMOS amp from a OM,
> originally built by KF8OD. Each package has the 2 devices in parallel, and
> the two packages are driven off the ends of a center-tapped 1:4
> transformer, bias applied to the center tap. The outputs go to yet another
> transformer and out the antenna.
> It's worked ok - the T/R relay quit so I changed it, but efficiency has
> been low on 160M. Once it heated up, a symmetrical spur came up, in-band
> but some 30 kHz or so from the op freq. Running into my relatively high-Q
> 160M antenna would drive my LP100A meter nuts for obvious reasons, although
> the SA showed the story.
> A thermal image showed the bypass caps on the power supply side of the
> bifilar drain choke were heating up, the T-200 powdered iron core to a
> lesser degree. I pulled the bifilar choke off and wound (2) separate drain
> chokes with 12 AWG enameled on Mix-31 Fair-Rite beads. (1/2" ID, an inch or
> so long) I didn't know if the high DC current would ruin the choke
> effectiveness, but I put them in to test. The new chokes run cool as a
> cucumber, the bypass caps no longer heat up and the efficiency is up
> substantially. (on 160 only) I don't know about the spur yet... Since I
> replaced the chokes I haven't been on the key long enough yet to find out.
> I may have time tonight to serenade the locals and see what happens.
> The last bit here is that the builder put a negative feedback circuit on
> both packages, 10 ohms 5W in series with .01 uF. I've seen data sheets from
> NXP and Ampleon that show that kind of feedback, and I've also seen schemes
> where the network was connected from the gate of each device (or package in
> this case) and ground - "gain control". The modules use 51 ohms
> and .01 uF from gate to ground. Does anyone have any info on the design of
> that network?  I know preventing low-freq oscillations is important with
> these devices, but I haven't seen much actual discussion on how to get
> there.
> Thanks,
> Jim N7CXI
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