[Amps] OK, here's a home brewing question. Class D amp, FET dead, time understanding?

[Chris Wilson]

Hello Manfred,

On Friday, January 13, 2017,  you wrote:

> Hi Chris,

>> OK, it's not actually a SMPS, but similar, a 136kW LF amp. I built it
>> some time ago.

> I hope you mean 136kHz, not kW! :-)

>> I had been looking at gate and drain
>> wave forms and saw nothing horrible to my eyes. 

> Well, your drain waveforms look quite horrible to me! You must be 
> getting strong harmonics on the output.

>> I then read up on
>> "dead time" the time neither device should be on to stop short
>> circuits or over current, using two channels and two probes. This
>> gives the waveform attached (I hope...) and to me there doesn't seem
>> to be any real dead time. Is it my measurement inabilities, my
>> misunderstanding of dead time concepts, or have I found an issue? 

> Well... indeed your driver circuit, using the complimentary outputs of a
> flipflop passed through simple gate drivers, provides no deadtime. But
> with the power FETs arranged as they are, you don't need any dead time
> at all! So that's no bug.

> Deadtime is needed whenever you have two transistors in series, such as
> in a half bridge circuit, and when also the transistors take longer to
> switch off than on (which is typical). But your transmitter is a 
> push-pull arrangement powered through a choke, CH1. If both FETs are 
> driven on at the same time, all that will happen is that they will share
> the current flowing in that choke, and that this current will slowly 
> increase, at a rate defined by the choke's inductance and the supply 
> voltage. So the choke limits the current that can flow while the two 
> FETs conduct at the same time, and thus nothing bad happens if their 
> conduction cycles overlap slightly.

> On the contrary, if there were a dead time, then the choke would force
> the current to flow even while both FETs are off, and that would drive
> both drains to a higher voltage, limited only by the capacitance to 
> ground, which in your circuit is given by the two 4n7 capacitors. 
> Basically these capacitances, together with the operating current, 
> define how fast the drain voltages would rise if both FETs turned off.
> This determines after how much deadtime the drain voltage would exceed
> the maximum allowed voltage for those FETs.

> So, in a circuit like this, dead time isn't necessary at all, and too 
> much dead time is not allowed.

 >> Even on reduced
>> voltage to the PA FET's I get one popping quite often, and I can see
>> no other issues, like bad antenna matching etcetera.

> I can see at least one issue, most certainly!

> One of them is your TX enabling method: When you switch off TX that way,
> you are cutting the 12V supply to the driver circuit, but you have a 
> 100µF capacitor on that supply! And your driver circuit consumes very 
> little current. So the voltage on that capacitor will drop slowly, and
> since those driver chips work down to 4.5V or even less, there will be a
> significant time in which they aren't driving your FETs on and off, but
> half on and then off! When they are half on, they dissipate a huge lot
> of power. It's perfectly possible that they exceed their safe operating
> area every time you disable the TX line, and that over time that damages
> the FETs until they blow up.

> Instead you should find a better way to make the TX switching. Such as
> switching the 100V supply. Or if the FETs used have enough avalanche 
> power capability to absorb the power stored in CH1, then you can safely
> disable TX by resetting the flipflop through the safety circuit input.

> Also make sure that you are correctly handling the thermal side of 
> things. At 1kW output, these FETs are probably dissipating a significant
> power, and need to be heatsinked well enough.  Many FETs die in the 
> hands of hams simply from totally banal overheating!

>> Where does "dead time" come from? Is it from the architecture of the
>> driver chips(s) itself / themselves? Or is external circuitry needed?

> Some driver chips have built-in fixed dead time, and in others it can be
> programmed by means of an external resistor, or less commonly a 
> capacitor. Typically driver chips intended for bridges or half bridges
> have this function.

> In other circuits it's implemented before the driver chips. For example,
> many pulse width modulator ICs, such as the very common TL494, allow 
> programming the dead time. Those that don't have a dedicated dead time
> control pin, control it by the clock capacitor value.

>> I see propagation delay figures cited, but I don't think this is the
>> same as dead time.

> No. When the propagation delay is the same for high-to-low and 
> low-to-high transitions, then there is no dead time. When a driver chip
> implements deadtime, the output low-to-high transition has a much longer
> "propagation delay" then the high-to-low transition.

>> On the drain waveform capture I am not sure what
>> the blip is before the drain voltage rises. Is that some dead time, or
>> an attempt for both devices to conduct together?

> My interpretation: The blip starts when the FET gets out of conduction,
> and ends when its opponent starts conducting and this propagates from 
> one drain to the other, via the delay of the 4n7 capacitors and the 
> coil. Only after some while does the voltage then really go up. This, 
> together with the very bad drain voltage waveform, makes me think that
> your tank circuit is totally out of tune! This looks like a class E 
> amplifier (not class D), but one that isn't tuned correctly!

>> I changed from a single dual output inverting gate driver chip type
>> TC4426 to two single output inverting chips type TC4452 in order to be
>> able to drive more powerful, higher gate capacitance MOSFET's in the
>> future. Maybe these have caused an issue, I had nothing like the same
>> failure rate before my mods.

> Hey, the TC4452 is non-inverting, while the TC4426 is inverting! And 
> when the 4013 flipflop gets a RESET signal in your circuit, both of its
> outputs go high. So, with the original chip, if the protection circuit
> activates, the transmitter is turned off by switching off both FETs. But
> with the chip you selected, the protection cirucit turns both FETs _on_
> at the same time, and that's sure to blow them up!!!

> You should have used the TC4451 instead, that's the inverting version!

> Manfred

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Hi Manfred, I cannot tell you how pleased I am that you have
responded. I have taken the liberty to bring the reply to direct
e-mail, I hope you don't mind? I have kept nearly all your posts to
the group in a separate folder as I have learnt something form every
one of your measured and considered postings, thank you!

Firstly I have asked a similar question on other forums, and direct to
the designer of this amp (which I admittedly have fiddled with...),
plus a designer who sells a board and component commercially, of
similar design. None have said I need no dead time, they have assumed,
like I have been doing, that it worls the same as a half bridge I
guess, and needs dead time.

I have misled you due to sloppy posting and a lack of pertinent
information. I do not use the FET that acts as a TX switch for RX/TX
switching. That FET is permanently in the conducting state and as I
normally run OPERA or WSPR I just let the exciter, a Kenwood TS-590
feeding 136kHz from it's low power (0dBm) output socket into a pre
amp and frequency doubler, feed the permanently on amplifier. Sorry,
the schematic I posted is very confusing. Secondly the driver chips I
have replaced the TC4426 dual output inverting chip with are two single
output TC4451's. I just (again sloppily) referred to them from the
data sheets's original file name. They are definitely the inverting
TC4451, although someone else told me it doesn't matter. I did realize
that it DID matter though, and ordered accordingly.


So given these corrections, do you think I should still be looking at
the output transformer? After the low pass filter the scope shows a
nice sine wave, but I admit a local to me ham does see a signal with
WSPR at 1500Hz on top of a dial frequency of 136kHz at 137.550 and
137.440kHz (two signals, the wrong one very well down, but he's only a
few miles away and only when I run with 100V to the PA FET's.

I am running it off a pair of big HP SMPS computer server supplies.
52V each, at many Amps. In series for full power, singly for low
power. Before I changed driver chips and added some additions to the
protection circuit I had few FET failures, even with them in series.

What I do sometimes see is using a "Scopematch" home brew box

http://ve7sl.blogspot.co.uk/2014/08/your-lf-stations-best-friend-scopematch_5.html

to show voltage and current against phase on my scope, is a funny
ramndom trace just as a TX sequence starts. FET failure most often
occurs just at the END of a WSPR TX sequence, for some reason. OPERA
seems kinder to FET life, again, fot=r some mysterious reason, but I
am sure it's not random.

Is there a way to check how the output transformer is performing out
of the circuit? I have a signal generator, a frequency counter, a
couple of scopes and a spectrum analyzer, but am less than proficient
with most of them. I also have an AIM4170 antenna analyzer. The LPF
stage feeds an impedance matching transformer outside, via co-ax, then
the transformer feeds a huge loading coil and the antenna is a big
horizontal loop I use for HF, with the vertical ladder line feeder
strapped together at its base, and fed from the top of the loading
coil which containers a trimmer coil in the form of a variometer. The
AIM4170 shows a good match to 50 Ohms (47 Ohms depending on weather
conditions) and the Scopematch shows good phase. The voltages on this
electrically tiny aerial are huge though.

Sorry for the diatribe, any advice greatly appreciated Manfred. When
it all works without a blow up I can get from here in the middle of
the UK into Asiatic Russia, Iceland, Italy etcetera, so it does have
some promise when fettled up a bit!

Here's the original article on this amp, it's the base station
version, I tried to add flip flops and inverters so the single and as
such ambiguous fault LED was replaced by three LED's to show which
safety circuit had tripped, and I replaced the Hall effect transistor
looking at the end of the ferrite rod CH1 is wound around for a small
Hall effect module that senses PA current and gives a rising voltage
to a comparator to trip the amp if current rises too high, it doesn't
seem to stop FET's blowing occasionally on low voltage, and frequently
on high voltage though.





-- 
Best regards,
 Chris                            mailto:chris at chriswilson.tv