[CQ-Contest] Re CW keying interfaces

[David Pruett]

jack schuster wrote:
> I have never seen a need for optoisolators and never heard of  a transistor failure in hundreds of interfaces I built. KISS!   JACK W1WEF 
> (keep it simple...)
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>   
There is a very good reason for using an optoisolator in a CW keying 
circuit.

The circuit which originated (I believe) with K1EA has the keying 
current return out of the emitter of the NPN transistor to ground 
through pin 1 of the LPT interface which is defined as the STROBE output 
from the port.  I've not been able to find a spec for this pin, but on 
most LPT interfaces I've seen it goes into some sort of LSI (large scale 
integrated) IC.  Lacking any spec, its hard to know whether this is a 
true open collector output or some sort of TTL/CMOS device.  In any 
case, it's not too hard to imagine exceeding an open circuit voltage, or 
closed circuit saturation current rating on such a port, depending on 
the actual voltage/current that's being keyed.

I believe that the reason for the use of this pin is to prevent the 
keying interface from keying the rig until the logging program actually 
starts.  On many computers, pin 17 goes high when the computer is turned 
on, and without pin 1 preventing the keying pin from being sunk to 
ground, the radio would key as soon as the computer is turned on.  Once 
the logging program starts, it asserts pin 1 low.

I've blown up this pin on at least one LPT port at K8CC using the simple 
single-NPN keying interface.  I don't think this is a major risk for CW 
keying, but many programs duplicate the same interface, but driven by 
pin 16 (and returned to pin 1) for PTT control by the logging program.  
It's not too hard to imagine that the PTT current of a transceiver might 
include the coil current for one or more relays which will likely 
overstress the port electronics connected to pin 1 trying valiantly to 
sink all this current to ground.

The good thing about using an optoisolator is that the port electronics 
connected to pin 1 only has to sink the port's drive voltage/current 
which comes from pin 17 and will not exceed 5VDC and a couple mA.  The 
keying current (CW or PTT) will be confined to the output portion of the 
optoisolator.

The bad thing about using an optoisolator is that most have transfer 
functions less than unity.  The typical NPN transistor has a beta (gain) 
of 20 or more, so the couple of mA coming from the LPT port pin 17 can 
cause the NPN to sink perhaps 40 mA or more thru the keying/PTT output.  
If the opto has a gain of 80%, then it can only sink 1.6 mA with the 
same pin 17 port drive.  Optoisolators are available with Darlington 
outputs having transfer functions of 2000% (which is in line with the 
gain of the generic NPN transistor) but these have a higher saturation 
voltage and thus might not be able to key the rig fully.

A really good approach is to connect the emitter of the NPN keying 
transistor directly to the LPT port common along with the return line of 
the keying cable, which confines the keying/PTT current to the 
collector-emitter path of the transistor.  To prevent the interface from 
keying the radio when the computer is first turned on, then use the 
signal from pin 1 to inhibit some logic between pin 17 and the base of 
the NPN transistor.  This is what the engineers from TopTen did in the 
DXDoubler SO2R box, and the result is that the LPT port is nicely 
protected from damage due to keying load currents.

Sorry for rambling on, but IMHO the discussion about a simple NPN vs. an 
optoisolator is missing the point.  It has more to do with avoiding 
damage to the LPT port than failures in the device itself.  Blowing up a 
cheap LPT card is bad enough, but if your LPT port is integrated into 
your motherboard then repair can be a major pain in the neck (i.e., a 
new motherboard).

73,

Dave/K8CC