[TenTec] Paragon Keying Problem

[Bwana Bob]

Mike:

Check the PLL alignment. It sounds like it is taking too long to lock.
Check the voltage on the major loop board. The test point is at the
junction of Q1 collector and Q3 collector. There are 4 VCO's that cover:

0.1 to 7.0 MHz (far right VCO can)
7.0 to 14.0 MHz
14.0 to 22.0 MHz
22.0 to 30.0 MHz (far left)

At the low end of each of the 4 bands, the VCO voltage will be about
2.75 and will increase to about 7.7 V at the high end. Also, if your
board has a pot on U3, adjust it for 3.2 V on the wiper.


			73,

			Bob WB2VUF


Michael Tope wrote:
> 
> Has anyone run into trouble with the keying on the
> Paragon I. On mine, it gets confused when I am
> trying to key it at between about 20 to 25 wpm
> and do a frequency offset (rit or split mode) at the
> same time. Seems that at higher speeds, the
> PLL stays locked to the transmit frequency
> between characters, and a low speeds it has
> time to switch smoothly back and forth between
> the TX and RX frequencies. Over the effected
> range, it tries to switch, but doesn't have enough
> time. As a result, the CW gets choppy and
> unintelligible. Unfortunately, when chasing DX,
> this speed range is oftentimes also the optimum
> speed for calling DX (especially on 160).
> The quick solution is to manually switch between
> VFOs, but this is getting old. Any suggestions?
> 
> 73 de Mike, W4EF..............................
> 
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