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Re: [Amps] Freescale LDMOS devices / load mismatch survival

To: amps@contesting.com
Subject: Re: [Amps] Freescale LDMOS devices / load mismatch survival
From: Steve Thompson <g8gsq72@gmail.com>
Date: Mon, 11 Mar 2013 08:01:57 +0000
List-post: <amps@contesting.com">mailto:amps@contesting.com>
The video is, indeed, impressive - but it could also give a false impression. The transistor operating spec. is 100us pulses at 20% duty cycle - 100us on, 400us off. Looking at the current drawn during the variable load pull test, it's not running cw. Also, the test is being done at 200MHz and ruggedness doesn't necessarily translate to lower frequencies for those thinking of hf applications.

At 100us long pulses, the die inside probably isn't reaching the peak temperature for any given dissipation which makes high VSWR survival easier.

F1JRD tested Freescale devices with all phases of high load VSWR running 10ms pulses, low duty cycle. They survived, so a trip circuit acting faster than that should protect them. I'd expect NXP parts to be similar.

Steve
Leigh, the idea of having a device without external means for
protection is intriguing. A device that can sustain such
repetitive abuse and continue to operate is really something.
As you said stated it could be done with standard methods,
however they do marginal SWR, and high current shutdown. If
you've seen the test video of the NXP device on Youtube, the
power output never shuts down, just simply sits in ready for
the mismatch to clear.


73, George, K4GVT

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