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Re: [Amps] LDMOSFET questions for insiders

To:, Doug Ronald <>, jeff millar <>
Subject: Re: [Amps] LDMOSFET questions for insiders
From: Manfred Mornhinweg <>
Date: Fri, 23 Nov 2018 21:48:12 +0000
List-post: <>
Doug, Jeff,

Ampleon has published on the topic, and is one of the few semiconductor companies who specify their avalanche energy at least for the BLF188XR LDMOS dual. They still use the UIS test which demonstrates that their LDMOS transistor has substantially better absorbed single pulse energy than a comparable VDMOS device. It also
 shows as you suspected, that avalanching the device has implications
beyond thermal. You might find the following white paper has some useful information:

Thanks, Doug. At least I get a number from that paper: Roughly 3 joule
for single event avalanching, at the highest current I might have. But
they stress that the single-pulse avalanching data is not valid when
bias is applied, so it's moot. Both for being single pulse, and for
being at zero bias. I will have to work from the SWR testing instead,
but that's much harder.

They also discuss the gate ESD diode's effects on class of operation
 when it is forced into conduction - could possibly move a class C to

Yes, but I'm not worried about that effect in my project. The drive
voltage I will use, along with the bias and the gate protection clamping
voltages of the devices considered, should not result in significant
gate protection current. Also I'm using a nice low impedance bias supply.

That paper mentions several other points that worry me. I always though
that the parasitic bipolar transistors in MOSFETs only turned on from
excessive drain voltage dv/dt. But this paper contains something that
confuses me. It says:

"The drain-source diode clamps the voltage across the LDMOS and the
parasitic bipolar sinks the excess current to the
substrate. For large sink currents, however, the drain-source voltage
exceeds the diode breakdown voltage and the parasitic
bipolar transistor can be triggered."

I cannot make full sense of this. I think there is a mix-up of several

That paper contains several other strange things too. One is the 41MHz
reference design, which claims obtaining 1200W output with 1:4 impedance
transformation on the output, and 50V supply. Even if the circuit
operates with a square wave, including all harmonics in the power
measurement, and if the MOSFET has zero RDSon, this would still only
allow 800W into a 50 ohm load. In practice, I wouldn't expect more than
700W saturated output, square wave. So if they actually get 1200W from
this circuit, they must be doing some additional impedance matching with
the PCB traces and capacitors at the drains, and there are some
capacitors visible in the photos that suggest this is the case - but
they don't mention it.

There are academic publications searchable through Google Scholar, but I found all the IEEE Explore articles wanted mucho dinero, and others wanted a registration and login to read more than the abstract...

I have found the same, and been put off by it.

Also many scholar publications read like a mathematical treatise rather
than a book about electronics.

The voltage rating is high enough to handle 100% reflected with any phase angle in 20% duty cycle pulse operation.

Jeff, the paper linked by Doug says Ampleon uses 10% duty cycle for the
SWR testing. Freescale's datasheet for the MRF1K50N instead indeed uses
20%. Anyway it's hard for me to derive the actual continuous avalanching
ruggedness from this data.

Effectively, as long as the High SWR trip can operation as fast the on pulse time, the amplifier is rugged to 100% reflected. I forget the rep rate of the pulses, but the trip circuit has 10's of msec.

The testing uses 50 or 100 microseconds, which means that the protection
circuit should be able to completely shut down the amplifier in less
than that time after the high SWR condition starts, to be certain to
make the device survive.

Also this data is valid for a specific test circuit, with the device on
a watercooled block, in low duty cycle mode, so it's very cool during
the SWR testing. But in ham amp it might be much hotter when the SWR
suddenly skyrockets. That forces the protection to be even faster.

So it's not 10's of milliseconds, but less than 0.1 millisecond!

Doing dynamic thermal impedance calculations, I arrive at typically 1ms
allowable reaction time, but that's assuming that the dissipation
capability is the same with and without avalanching - and now I know
that this isn't the case! So it seems that the <100 microsecond figure
is the one we should take, to be safe against destruction from avalanching.

Avalanche can occur unevenly across the die and result in uneven heating. The power limit is not total dissipated, rather quite a bit
 less, due to the risk of localized damage.

Yep. And from the data above, intuitively it looks like this effect
causes roughly a tenfold reduction in safe dissipation capability, when
avalanching happens.

An amp with fast trip will not need know the details of that.

If it's faster than 100 microseconds, yes. It seems reasonably easy to
make a protection circuit as fast as that. My problem is that my project
goes far beyond this! I do NOT want to make an amp that always has to
work into a 1:1 SWR, with the help of an antenna tuner, and shuts down
instantly when the SWR is, say, 1.3:1. My point is that any given SWR
can be caused by an infinite number of different impedances, and many of
them do not result in dangerous operating conditions. So I want to know
what the actual operational limits are for LDMOSFETs, and design my
protection circuit so that it allows operation into significantly higher
SWR, as long as the specific load impedance does not result in
overstressing the transistor. I think that this would be far more
practical for everyday ham use, instead of requiring very low SWR for

As things look now, it seems that I will have to add a rectifier at the
drains to sense the peak drain voltage, and use this as one more input
into the protection circuit. Shutting down the amp quickly if the drain
voltage peaks get close to the breakdown voltage, by allowing operation
even at higher SWR, as long as neither the drain voltage nor the drain
current nor the dissipation exceed safe levels - where the maximum safe
dissipation depends on the cooling system used.

Body diodes in switching power supply MOSFETs are slow. LDMOS is presumable the same. So, not fast enough for 100 KHZ switching PS and not nearly fast enough for RF.

That's what I suspect too, but it would be nice to know for certain.

A MOSFET with gate drive will conduct in both directions, negative current is not a problem...presumably LDMOS is the same.

Yes - but with a reactive load it's very possible that the load plus LP
filter forces a negative drain current at a part of the waveform where
the drive has turned the MOSFET off, or the gate voltage is already too
low to conduct the drain current forced by the load plus filter. This
can result in turning on the body diode, and I did it on purpose with a
test amplifier using cheap switchmode MOSFETs on 80 meters. The
observable symptom is very high current consumption with little power
output, and thus very high dissipation.

Since big LDMOSFETs are expensive, I would like to know as much as
possible in theory, before starting experiments with them. I'm quite
happy using $1 switchmode FETs in possibly destructive testing, but not

The FET can handle 100% reflected with any phase angle, one of those is max drain current.

There is yet another trouble with my project: The manufacturer's
ruggedness testing relies on strictly limited drive. Some use 3dB
overdrive, others perhaps 5dB overdrive. Perhaps some LDMOSFETs are
tested with no overdrive. In any case, the drive limits the maximum
current the devices can possibly conduct. So, as long as the drive is
kep low enough, overcurrent is impossible. But my project requires
considerable overdrive, and all tolerances in drive power across bands
need to be from about 5dB overdrive upwards, to keep my amp nicely
saturated and efficient. A worst case on some band might end up with
10dB overdrive, far exceeding the level used in the manufacturer's
ruggedness testing. That's why max drain current is important to me. I
need to have a fast current sensor, and shut down the amp if the drain
current exceeds the safe level. For that I need to know what the safe
level is.

Just stay within the pulse limits.

Not desirable in my project. I want a "contoured" protection scheme,
that allows operation in all SWR conditions that are safe, even some
pretty high SWR ones.

The RF current does not distribute evenly acoss the 1000's of
parallel FETs, but over the thermal time constant of the die,
differential heating and negative temp coefficient provides the
feedback to balance the currents.  But instantaneously, localized
heating can blow up a corner of the die.

The simple question is: How much. The feeling I get is that continuous avalanching dissipation might have to be limited to roughly 10% of normal dissipation, but probably this depends on many factors.

> I hope this helps.

Yes, it does, in more ways than what's obvious. An important one is triggering more thoughts.

As a refresher, the amp I'm talking about is the final stage of an SDR using envelope tracking, to achieve high efficiency. So the final stage operates in saturation, the drive level is always about 6dB higher than where clipping starts, and the 50V supply goes through a modulator circuit (in class D).

My current plan for a protection scheme is this: Having fast current sensors at the power supply, used to measure power input (at fixed 50V), and after the modulator (measuring drain current). Also a directional coupler delivering forward and reflected voltage signals. And now I see that I need to add drain peak voltage detectors. These five signals go into the protection processor, which is a small microcontroller because I need several multiplications and divisions, which are cheaper to do in a microcontroller than in analog multipliers.

This processor can do the following:

- Calculate forward and reflected power, by squaring the voltages delivered by the directional coupler;

- Calculate effective power delivered to the load, as the difference between forward and reflected power;

- Calculate actual power dissipation, as supply power minus effective output power.

And now it can reduce drive, or shutdown the transmitter, whenever the dissipated power, drain current or drain peak voltage get close to critical.

It can also calculate SWR, and shut down at a certain SWR leve, but this would not be strictly necessary, allowing operation under some conditions of elevated SWR.

To have a chance of implementing this without burning out several $200 LDMOSFETs during testing, I need to get as much info about their absolute maximum ratings as possible! Since I have more time and patience than $$$, I hope to achieve it without burning out any device.


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