[TowerTalk] Coax Lengths for Stacked Yagis

[Wayne Kline]

MY reason for using  odd multiples of ¼ wave feed line. Was all my antennas are either Beta match or direct feed OWA.   Purely resistive loads   not capacitive as in a beta match.

Speaking  to Ken K1EA many years ago.. and others.    he was the one who strengthened the notion .  @ odd multiply 1/3 wave transmission line Voltage in minimum and current is maximum.



Wayne W3EA

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From: TowerTalk <towertalk-bounces at contesting.com> on behalf of Wes Stewart <wes_n7ws at triconet.org>
Sent: Friday, May 4, 2018 4:07:32 PM
To: Richard (Rick) Karlquist; towertalk at contesting.com
Subject: Re: [TowerTalk] Coax Lengths for Stacked Yagis

I probably should have been a little more specific; there are some special case
exceptions.

Roy Lewallen says on page 6-15 in my 22nd Edition of the ARRL Antenna Book:

"The only cases in which the current (or voltage) delay is equal to the electrical
length of the line are
1) When the line is flat; that is, terminated in a purely
resistive load equal to its characteristic impedance;
2) When the line length is an integral number of half
wavelengths;
3) When the line length is an odd number of quarter
wavelengths and the load is purely resistive; and
4) When other specific lengths are used for specific load
impedances."

Wes


On 5/3/2018 9:24 PM, Richard (Rick) Karlquist wrote:
> Isn't it true that for lines that have a length
> that is any multiple of a quarter wave,
> the phase shift when matched is the same as when mismatched?
>
> Otherwise, (1) is correct AFAIK.
>
> Rick N6RK
>
> On 5/3/2018 9:06 PM, Wes Stewart wrote:
>> Another point or two and then I'll shut up.
>>
>> 1)  The expected phase shift in a line is only achieved when the line is
>> matched.
>>
>> On 5/3/2018 7:28 PM, Wes Stewart wrote:
>>> Quarter wavelength lines have the magical property that the output current
>>> is equal to the input voltage divided by the line Zo.  So with multiple
>>> inputs tied together, and obviously having the same voltage, the output
>>> currents will be equal.
>

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