Le 04/12/2018 à 17:28, Manfred Mornhinweg a écrit :
Daniel,
thanks for all your input and links! It has kept me busy and learning
for two days.
Your project is a great task, congratulations.
I just hope I can ever bring it to a successful end!
The main cause of transistors' failing is drain (collector)
over-voltage which often translates by over-current or avalanche.
The more I read up, the more it looks like I have to take all measures
I can to strictly avoid drain overvoltage. I had hoped that I could
trust the "extra rugged" LDMOSFETs to safely clamp overvoltage to some
extent, possibly enough to keep the amplifier running with high SWR as
long as the dissipation doesn't become excessive, but all you wrote
and what I could see in those articles discourages me from that idea.
For example, on of the articles talks about overvoltage failures
happening either on the body of the chip or at its periphery.
Obviously any breakdown at the periphery will happen only over a small
area, and thus concentrate a lot of power dissipation there, causing
failure even at low dissipated power levels. So it looks like I need
to at least monitor drain peak voltage to activate the protection, and
perhaps even clamp it externally.
At this point I hope that at least I can trust the LDMOSFET's
ruggedness to handle brief overvoltages until the protection kicks
in, but it's not encouraging to read Microsemi's paper saying that
always some devices will fail during high SWR testing...
It is very difficult to limit over-voltage even if you limit the
input power, you have to take care of load impedance (swr), overshoot
of ALC, spurious signals, di/dt.
That's my problem. Any load impedance can happen on the antenna port,
the low pass filters transform these impedances, the non-zero line
length of the impedance transformation circuit transforms it further,
and to this we must add that the amp will have to work over 4 octaves
into at least half a dozen filters, which makes drain waveform control
an impossible task.
Externally clamping drain voltage is difficult due to the high current
and low impedance involved. "Active clamping" through negative
feedback that drives the transistor on when the voltage goes up can
clamp the voltage pretty well, but is somewhat hard to implement
without risking gate overvoltage. And of course it puts more
dissipation into the transistor, and may increase risk of latch-up. I
don't fully understand the last point at this time, I mean, how
exactly latch-up happens, and under what exact conditions.
> The second: Temperature, in amateur use, must
not be a problem in a well designed amplifier.
Specially in my amplifier, which is supposed to have a high
efficiency, thermal design is easier than in a linear class AB
amplifier. But that said, I must also say that many high power
LDMOSFET ham amplifiers have extremely marginal thermal designs, often
running the LDMOSFET dies at or even above the absolutely maximum
rated temperature, resulting in high risk of failure. I have also
noticed that many ham experimenters, and probably also some designers
in the industry, don't fully understand thermal design. They mount the
device on a copper heat spreader, mount that on a big heatsink with
fans, and then they think they can safely dissipate a kilowatt or more
of heat. And unfortunately this isn't the case! This leads to many
hams killing LDMOSFETs simply by overheating them.
I thought about temperature range.
I agree with you, and increasing power density is leading to more
difficult tasks.
The problems with SWR are: that with a sudden SWR (open or short
antenna feeder), before the security device begins to respond,the
transistor sees infinite SWR.
And when we asked different manufacturers "how much time your device
can sustain an infinite vswr" their response where elusive.
This is largely what motivates my questions here: How much energy can
a given LDMOSFET safely clamp, how much power or current can it clamp
for how much time, and how much power or current can it clamp
continuously with no time limit in CW (not pulsed) operation.
If the answer is "zero", then no protection circuit alone is good
enough. The amplifier needs to be designed to actively suppress all
drain voltage peaks, for example through carefully designed,
non-linear drain-gate feedback. If instead the answer is that the
transistor can clamp a well defined amount of energy, with certain
current and time limits, then one can do without that non-linear
feedback, and use a fast-enough protection circuit that shuts down the
amp. And what's important to me too: If the transistor can
continuously clamp a certain amount of current, then I can allow
operation into some high SWR conditions. If it cannot, then I have to
shut it down whenever the SWR goes up, making it less practical.
That's why I want so much to know these data!
During this High SWR does the transistor see high voltage or drains
high current. High current is not a problem but high voltage is.
I wonder if high current is still no problem even when the amplifier
is overdriven, say, by 6dB. When the drive is just right for full
linear output, the transistors cannot conduct more than the normal
current, so of course high current isn't a problem. But when there is
6dB (or perhaps more!) excess drive in a saturated amplifier, the
transistors can conduct twice or more of the normal current. Will they
survive that too? For how long? If I correctly understand what happens
with the parasitic bipolars in a MOSFET, drain current above a certain
limit can turn on the bipolar transistor in a few cells, and that
causes instant failure. How much drain current is guaranteed not to
cause this problem, in a given transistor? Many LDMOSFET datasheets
don't state an absolute maximum drain current!
Note that all the ruggedness testing for the datasheets is done with
well-controlled drive, and NEVER with high-efficiency, moderately
overdriven amplifiers!
Per various datasheets, they withstand a 65:1 SWR ( considered as
infinite) at nominal pulsed power in class AB during 100 µs - and I will
add: on a 50 ohm load, transistor mounted on a cold plate as usually
they do. I think, within those optimistic conditions, you need a
protection triggering in less than 100 µs.
Your idea to monitor vds is paramount and rather easy up to few
hundred MHz with a well shielded resistive divider terminated with 50
ohm connected to an RF cold ground.
Yes, but it's useful only if the transistors can safely clamp
overvoltage for some time, but cannot clamp it for a long time. That
allows triggering the protection if a sudden SWR increase causes high
drain voltage spikes. If instead a transistor cannot safely clamp huge
spikes for long enough, it's pointless to activate the protection
afetre the transistor has already failed... And if it can clamp
overvoltage indefinitely, as long as there is no overheating, then I
don't need to measure drain voltage at all, instead I can simply
monitor the dissipated power to implement full protection.
VLF to MW band transmitters which use switched amplifiers in class D
monitor the sign of the reactance to protect mosfets.
That's to keep the transistors in zero voltage switching mode, I
suppose. Those transmitters often handle many kilowatts of RF power,
while having dissipation capability of only 1kW or less, since they
have such high efficiency that they normally don't need more
dissipation capability. Of course any reduction in efficiency is
critical for them. In my amplifier this will be less critical, because
I intend to have a relatively high dissipation capability built-in,
for increased reliability, even if in normal operation the dissipation
should be rather low.
I have also seen MRF157s failing in the driver of a big SW broadcast
transmitter when there was a flash in the tube. The tube was
protected by switching off the solid state modulator. (Formerly
protection used ignitrons)
A clipper was then added at each transistor drain to limit induced
voltage under Vds max and problems were gone.
Ah, I suspect that those failures were caused by excessive inductance
in the drain circuitry, and shutting down the drivers by cutting off
the bias or the drive! That would cause a huge inductive spike on the
drains.
One shouldn't use more drain inductance than strictly necessary, AND
one should make sure to pull down the gates slowly enough so that the
drain overvoltage caused by that inductance remains manageable.
Yes, but according to frequency it is not easily manageable.
Before connecting your PWM modulator make a full DC sweep of your
amplifier because I remember when we began to design with envelope
tracking (not doing EER or Kahn but tracking few volts above the
strictly necessary drain voltage; the amplifier being in class AB)
the transistor was going into oscillation around 20V DC.
This mosfet (the same generation as the one you planed to use, but he
was climbing to 900 MHz) went into oscillation when the bias was
applied before drain voltage.
Usually the bias is applied when the drain voltage is about 80% under
nominal value to prevent that, but here it is not possible.
This point worries me a lot. I have seen a few (very few) previous
mentions of this LDMOSFET instability happening at low drain voltages,
and I have never found a good explanation for it. Do you happen to
know some more about this? I have seen amplifiers designed with bias
circuits that come on only when the drain supply voltage is above 80%
of nominal, but of course, as you say, I cannot do that. If a device
exhibits this form of instability, and if the instability is
internally caused and cannot be fixed by external feedback or other
external means, than that device simply can't be used in my project.
If this phenomenon affects all LDMOSFETs, then I can pack up and
redesign my project around a pair of 3-500Z...
HI ! the 3-500Z, great for peace of mind!
I don't remember I had seen exactly this with bipolars. What I have seen
was low frequency oscillation (~ 500 kHz) during peak modulation when
the antenna coupler was adjusted a narrow bandpass manner. This never
killed the transistors when it arrived.
In a 1973 publication of CTC "Solid Circuits" they advice at initial
amplifier turn-on to look for spurious responses at low frequencies and
beginning at low voltages (I will add allways with current limiting).
According to them the cause is high gain at low frequencies and a right
impedance to make an oscillator. They sugested negative feedback and/or
present a resistive impedance at low frequencies for input and output.
Polyfet have adapted parts of this document in their faq:
http://www.polyfet.com/faq.htm
I cured such oscillation on a 200 MHz amp having a spurious at 5 MHz in
replacing an SMD grid decoupling capacitor by a leaded one with a
ferrite bead to broaden the supposed resonance. This case is generally
lethal because spurious is outside of the output bandpass.
In the 2 LDMOS cases I saw, the oscillation was at a rather high
frequency and the grid damping resistors used with older generations did
nothing unless decreasing gain.
But perhaps you will not have to bother with that, it was with UHF
amplifiers using LDMOS having around 20 dB gain.
I don't know why this happen.
I advice you to do the test using the current control of your power
supply to sweep the all range voltage while controlling the stability.
I will certainly do that.
Don't forget to design with the decoupling capacitors compatible with
your PWM filter; you may decrease their values severely leading?
perhaps to instabilities.
Yes, I'm very aware of that. The last capacitor of the PWM filter is
actually the drain decoupling capacitor of my RF amp. Physically this
will be a row of roughly 20 ceramic capacitors, totalling slightly
under 1 microfarad, placed in extreme proximity to the drains and the
source return. I would like to use C0G/NP0 ceramic, but it's not too
easy to find in the necessary ratings, so the capacitors I have on
hand have X7R dielectric, with 100V rating, 1206 size. Do you have any
idea about their suitability in terms of RF current handling, and
capacitance stability when exposed to the modulated voltage? According
to what I can dig out of datasheets, they should be acceptable, and
some tests done by other hams seem to confirm that, but I haven't done
the final test myself yet.
I have not done that but it's worth to try but I would prefer the 1210
package physically stronger they have less tendency to break if the PCB
is bent a little.
Since I cannot use high capacitances in the drain circuit,
low-frequency stability must come from negative feedback and from
resistive gate loading, both of which must remain effective down to
very low frequencies.
Since I'm a crazy guy, I'm planning to put the drive and predriver on
the same board, for a total of nearly 60dB gain, and I want to see if
I can achieve stability... But I'm mentally prepared to cut the board
in two, if necessary! :-)
It must be possible with a good ground reference and a not too compact
design (at the beginning). But the great modulating power could be a
problem with ground loops.
I think you will need some linearity correction mostly for low voltages.
From 20 V to 50 V the linearity is fair.
The good thing about integrating this amplifier into an SDR is that
linearity correction of both amplitude and phase, through adaptive
predistortion, is a part of the basic features of the SDR section. On
the hardware side it only requires feeding back a sample of the output
signal into one of the SDR's receivers. All the rest of the job is
done in software, and this software is available for free.
Concerning overdrive as I remember (5 to 6 years ago) in Digital TV
(OFDM) there was around 6 dB clipping and RF peaks always around 2x
Vd while? with adaptive linearity correction peaks were beyond vgs max!.
On HF the gain of an LDMOSFET is higher, so one can have significant
overdrive without having to exceed Vgs max. If my calculations are
right, I will have at least 2V headroom between the absolute maximum
possible drive voltage peak plus bias, and the Vgsmax. Roughly the
same headroom, or a little more, with Vgsmin.
Due to fast acting, your primary protection MUST be hardware for SWR,
over-voltage, over-current and overdrive or ALC. The microcontroller
is for flavor and management of the slow events.
It depends on how fast the protection really needs to be. If I use a
cheap PIC, like the PIC18F886 I have in stock because I use it in many
projects, then every 10-bit analog-digital conversion takes around 2
microseconds, and the processor can execute 5 instructions per
microsecond. AD conversion and CPU processing can run in parallel, but
an event like an antenna failure needs to propagate first through AD
conversion and then through processing. With a well-written program I
think I can get a reaction time of roughly 50 microseconds. That's of
course slower than what an analog circuit could do, but if 50
microseconds is fast enough, then I don't need the expensive analog
multipliers. Until recently I thought that even 200 microseconds was
fast enough, but the more I learn, the more I doubt...
And I do not intend to use the microcontroller for flavor. I won't put
a display on it. If I use it, it will be a little black box hidden
deep in the circuit, doing a very basic slave job. Just the
computations required for the protection system. I don't think I will
need it for anything else, because the SDR does all the other
functions, including things like TX/RX sequencing.
Even the digital Icoms 7300, 7610 use direct analog control for ALC
and SWR.
But they don't compute SWR in the protection circuit, let alone
dissipation power!
Also, you can dig interesting informations here:
http://www.highfrequencyelectronics.com/index.php?option=com_content&view=category&layout=blog&id=47&Itemid=145
https://www.highfrequencyelectronics.com/Dec10/HFE1210_Brounley.pdf
http://www.highfrequencyelectronics.com/Apr04/HFE0404_Brounley.pdf
http://www.highfrequencyelectronics.com/Sep08/HFE0908_Grebennikov.pdf
http://www.highfrequencyelectronics.com/Jun10/HFE0610_Andrei_Part2.pdf
https://www.microsemi.com/document-portal/doc_view/133846-vswr-testing-of-rf-power-mosfets
I did. Thanks!
And if you have classical amps and want to play with:
http://www.highfrequencyelectronics.com/Jun04/HFE0604_Gutierrez.pdf
At least it works with old Mosfets like BLF 278 in class AB
Thanks to SDR, I don't need such a complex correction system.
I hope this helped you a little.
Yes, it did! But I'm still looking for more information, specially for
detailed, hard data on LDMOSFET ruggedness, and body diode behaviour.
Manfred
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Visit my hobby homepage!
http://ludens.cl
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Daniel, F6BRD
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